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| PRELIMINARY CY2X013 LVDS Crystal Oscillator (XO) Features Functional Description The CY2X013 is a high performance and high frequency Crystal Oscillator (XO). The device uses a Cypress proprietary low noise PLL to synthesize the frequency from an integrated crystal. The CY2X013 is available as a factory configured device or as a field programmable device. Low Jitter Crystal Oscillator (XO) Less than 1 ps Typical RMS Phase Jitter LVDS Output Output Frequency from 50 MHz to 690 MHz Factory Configured or Field Programmable Integrated Phase-Locked Loop (PLL) Output Enable or Power Down Function Supply Voltage: 3.3V or 2.5V Pb-free Package: 5.0 x 3.2 mm LCC Commercial and Industrial Temperature Ranges Logic Block Diagram 4 CRYSTAL OSCILLATOR LOW-NOISE PLL OUTPUT DIVIDER PROGRAMMABLE CONFIGURATION CLK 5 CLK# 1 OE/PD# 6 VDD 3 VSS Pinout Figure 1. Pin Diagram - 6-Pin Ceramic LCC OE/PD# 1 DNU 2 VSS 3 6 VDD 5 CLK# 4 CLK Table 1. Pin Definitions - 6-Pin Ceramic LCC Pin 1 I/O Type Description CMOS Input Output Enable Pin: Active HIGH. If OE = 1, CLK is enabled. Power Down Pin: Active LOW. If PD# = 0, the device is powered down and the clock is disabled. The functionality of this pin is programmable CLK, CLK# LVDS Output Differential Output Clock DNU - Do Not Use: DNU pins are electrically connected, but perform no function VDD Power Supply Voltage: 2.5V or 3.3V VSS Power Ground * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised June 15, 2009 [+] Feedback Name OE/PD# 4, 5 2 6 3 Cypress Semiconductor Corporation Document Number: 001-10261 Rev. *B PRELIMINARY CY2X013 Programming Description The CY2X013 is a programmable device. Before being used in an application, it must be programmed with the output frequencies and other variables described in a later section. Two different device types are available, each with its own programming flow. They are described in the following sections. Programming Variables Output Frequency The CY2X013 can synthesize a frequency to a resolution of one part per million (ppm), but the actual accuracy of the output frequency is limited by the accuracy of the integrated reference crystal. The CY2X013 has an output frequency range of 50 MHz to 690 MHz, but the range is not continuous. The CY2X013 cannot generate frequencies in the ranges of 521 MHz to 529 MHz and 596 MHz to 617 MHz. Field Programmable CY2X013F Field programmable devices are shipped unprogrammed and must be programmed before being installed on a printed circuit board (PCB). Customers use CyberClocksTM Online Software to specify the device configuration and generate a JEDEC (extension .jed) programming file. Programming of samples and prototype quantities is available using a Cypress programmer. Third party vendors manufacture programmers for small to large volume applications. Cypress's value added distribution partners also provide programming services. Field programmable devices are designated with an "F" in the part number. They are intended for quick prototyping and inventory reduction. The software is located at www.cyberclocksonline.com. Pin 1: Output Enable or Power Down (OE/PD#) Pin 1 is programmed as either Output Enable (OE) or Power Down (PD#). The OE function is used to enable or disable the CLK output quickly, but it does not reduce core power consumption. The PD# function puts the device into a low power state, but the wake up takes longer because the PLL must reacquire lock. Industrial versus Commercial Device Performance Industrial and Commercial devices have different internal crystals. They have a potentially significant impact on performance levels for applications requiring the lowest possible phase noise. CyberClocks Online Software displays expected performance for both options. Factory Configured CY2X013 For ready-to-use devices, the CY2X013 is available with no field programming required. All requests are submitted to the local Cypress Field Application Engineer (FAE) or sales representative. After the request is processed, the user receives a new part number, samples, and data sheet with the programmed values. This part number is used for additional sample requests and production orders. The CY2X013 is one time programmable (OTP). Phase Noise versus Jitter Performance In most cases, the device configuration for optimal phase noise performance is different from the device configuration for optimal cycle to cycle or period jitter. CyberClocks Online Software includes algorithms to optimize performance for either parameter. Table 2. Device Programming Variables Variable Output Frequency Pin 1 Function (OE or PD#) Optimization (Phase Noise or Jitter) Temperature Range (Commercial or Industrial) Document Number: 001-10261 Rev. *B Page 2 of 7 [+] Feedback PRELIMINARY CY2X013 Absolute Maximum Conditions Parameter VDD VIN[1] TS TJ ESDHBM JA[2] Supply Voltage Input Voltage, DC Temperature, Storage Temperature, Junction ESD Protection (Human Body Model) Thermal Resistance, Junction to Ambient JEDEC STD 22-A114-B 0 m/s airflow Relative to VSS Non operating Description Condition Min -0.5 -0.5 -55 -40 2000 64 Max 4.4 VDD+0.5 135 135 Unit V V C C V C/W Operating Conditions Parameter VDD TPU TA 3.3V Supply Voltage Range 2.5V Supply Voltage Range Power Up Time for VDD to Reach Minimum Specified Voltage (Power Ramp is Monotonic) Ambient Temperature (Commercial) Ambient Temperature (Industrial) Description Min 3.0 2.375 0.05 0 -40 Typ 3.3 2.5 - - - Max 3.6 2.625 500 70 85 Unit V V ms C C DC Electrical Characteristics Parameter IDD[3] Description Operating Supply Current Condition VDD = 3.6V, OE/PD# = VDD, output terminated VDD = 2.625V, OE/PD# = VDD, output terminated ISB VOD VOD VOS VOS IOZ VIH VIL IIH IIL CIN [4] Min - - - 250 - 1.125 - -35 0.7*VDD - Typ - - - - - - - - - - - - 15 Max 125 120 250 450 50 1.375 50 35 - 0.3*VDD 115 50 - Unit mA mA A mV mV V mV A V V A A pF Standby Supply Current LVDS Differential Output Voltage PD# = VSS VDD = 3.3V or 2.5V, RTERM = 100 between CLK and CLK# Change in VOD between complementary VDD = 3.3V or 2.5V, RTERM = 100 output states between CLK and CLK# LVDS Offset Output Voltage VDD = 3.3V or 2.5V, RTERM = 100 between CLK and CLK# Change in VOS between complementary VDD = 3.3V or 2.5V, RTERM = 100 output states between CLK and CLK# LVDS Output Leakage Current Input High Voltage Input Low Voltage Input High Current Input Low Current Input Capacitance, OE/PD# pin Input = VDD Input = VSS OE/PD# = VSS - - - Notes 1. The voltage on any input or I/O pin cannot exceed the power pin during power up. 2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. 3. IDD includes ~4 mA of current that is dissipated externally in the output termination resistors. Document Number: 001-10261 Rev. *B Page 3 of 7 [+] Feedback PRELIMINARY CY2X013 AC Electrical Characteristics[4] Parameter FOUT FSC FSI AG TDC TR, TF TOHZ TOE TLOCK Description Output Frequency[6] Frequency Stability, Commercial Devices[5] Frequency Stability, Industrial Devices[5] Aging, 10 Years Output Duty Cycle Output Rise and Fall Time Output Disable Time Output Enable Time Startup Time F <= 450 MHz, measured at zero crossing F > 450 MHz, measured at zero crossing 20% and 80% of full output swing Time from falling edge on OE to stopped outputs (Asynchronous) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) Time for CLK to reach valid frequency measured from the time VDD = VDD(min) or from PD# rising edge FOUT = 106.25 MHz (12 kHz to 20 MHz) VDD = min to max, TA = 0C to 70C VDD = min to max, TA = -40 to 85C Condition Min 50 - - - 45 40 - - - - Typ - - - - 50 50 350 - - - Max 690 35 55 15 55 60 - 100 100 10 Unit MHz ppm ppm ppm % % ps ns ns ms TJitter() RMS Phase Jitter (Random) - 1 - ps Switching Waveforms Figure 2. Output Voltage Swing CLK# VOD1 CLK VOD = VOD1 - VOD2 Figure 3. Output Offset Voltage VOD2 CLK 50 50 CLK# V OS Figure 4. Duty Cycle Timing CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Notes 4. Not 100% tested, guaranteed by design and characterization. 5. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, and variation from temperature and supply voltage. 6. This parameter is specified in CyberClocks Online software. Document Number: 001-10261 Rev. *B Page 4 of 7 [+] Feedback PRELIMINARY CY2X013 Figure 5. Output Rise and Fall Time CLK# 20% TR 80% 80% 20% TF CLK Figure 6. Output Enable and Disable Timing OE VIL VIH TOHZ CLK TOE High Impedance CLK# Termination Circuits Figure 7. LVDS Termination CLK 100 CLK# Document Number: 001-10261 Rev. *B Page 5 of 7 [+] Feedback PRELIMINARY CY2X013 Ordering Information Part Number[7] Pb-Free CY2X013FLXCT CY2X013FLXIT CY2X013LXCxxxT CY2X013LXIxxxT Field Programmable Field Programmable Factory Configured Factory Configured 6-Pin Ceramic LCC SMD - Tape and Reel 6-Pin Ceramic LCC SMD - Tape and Reel 6-Pin Ceramic LCC SMD - Tape and Reel 6-Pin Ceramic LCC SMD - Tape and Reel Commercial, 0 to 70C Industrial, -40 to 85C Commercial, 0 to 70C Industrial, -40 to 85C Configuration Package Description Product Flow Package Diagram Figure 8. 6-Pin 5.0 x 3.2 mm Ceramic LCC 0.50 SIDE VIEW 1.30 Max 2.54 TYP. 0.64 TYP. 0.10 R REF. TYP. TYP. 0.20 R REF. 4 5 6 5.0 0.32 R INDEX 7 10 TYP. 9 8 3 2 1 TOP VIEW BOTTOM VIEW Dimensions in mm General Tolerance: 0.15MM Kyocera dwg ref KD-VA6432-A Package Weight ~ 0.12 grams Note 7. "xxx" is a factory assigned code that identifies the programming option. Document Number: 001-10261 Rev. *B 0.10 REF. 001-10044-** 0.45 REF. 1.27 Page 6 of 7 3.2 1.2 TYP. [+] Feedback PRELIMINARY CY2X013 . Document History Page Document Title: CY2X013 LVDS Crystal Oscillator (XO) Document Number: 001-10261 Rev. ** *A ECN No. 504518 2705638 Orig. of Change RGL KVM/AESA Submission Date See ECN New data sheet Description of Change 05/13/2009 Removed pull up resistor on pin 1 Pin 2 changed from NC to DNU Added description of frequency range gaps Removed frequency stability as a programming option; added phase noise / jitter optimization Max storage temperature changed from 150 to 135C Max junction temperature changed from 125 to 135C Removed flammability and moisture sensitivity specs Added thermal resistance data IDD increased (100mA to 120 mA), conditions changed, and separate spec added for 2.5V supply Changed IDD values and conditions Standby current changed from 1mA to 250A Changes to IIL and IIH Added CIN spec Changed frequency stability and aging specs Relaxed duty cycle spec added for >450 MHz Removed period jitter spec Revised switching waveform figures 06/15/09 Minor ECN to post data sheet to external web *B 2718898 WWZ Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-10261 Rev. *B Revised June 15, 2009 Page 7 of 7 CyberClocks is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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